The present invention relates to encoding and decoding apparatus for variable length, run length limited binary ccdes in computing apparatus. More particularly, the present invention relates to integrated apparatus for encoding and decoding of binary data in accordance with variable length, run length limited codes in which three code bits correspond to two data bits for increasing storage densities in computer online mass storage subsystems, such as rotating disk data storage devices.
It is known to use variable length, zero run length limited coding processes in order to increase the density with which binary data may be recorded on rotating magnetic media storage disks, and similar applications. In such applications, a binary ONE represents a magnetic flux transition (or other change of state) while a binary ZERO represents no change of magnetic state or condition. Adjacent ONEs (or changes of state) are ideally separated by some minimum number of ZEROs by the coding process in order to reduce the undesirable effects upon magnetic media of unduly crowded adjacent flux transitions (called "pulse crowding").
On the other hand, since reliable data recovery from magnetic storage media depends upon relatively frequent occurrences of flux transitions or changes of state in order to enable synchronization of decoding and data recovery apparatus, some maximum length of consecutive zeros (called "zero run length") is implemented as some small integer, usually less than ten. An ideal code for a particular application results in a compromise between the code rate (i.e., the number of code word bits per data bit) and the transition interval between flux transitions: the smaller the code rate, the higher the aerial data storage density; and, the longer the run length of zeros the lesser the effect of pulse crowding and resultant distortion and error in the decode process.
A theoretical explanation as well as a discussion of practical advantages and benefits of a code employing a code rate of three code bits to two data bits, a run length of zeros between one and seven, and a variability factor of two, is set forth in an article entitled "An Optimization of Modulation Codes in Digital Recording" by T. Horiguchi and K. Morita, in IEEE Transactions on Magnetics, Vol. MAC-12, No. 6, Nov. 1976, pp. 740-742.
An implementation of the principles described in the above-referenced article is found in a later U.S. Pat. No. 4,337,458 to Cohn, Jacoby and Bates, entitled "Data Encoding Method and System Employing Two-Thirds Code Rate with Full Word Look-Ahead". That prior patent described separate encoding and decoding apparatus for encoding and decoding a somewhat cumbersome three to two code which did not employ encode and decode logic-minimized state machines. Rather, the apparatus disclosed in that patent had the drawback of complexity in requiring the use of look up values stored in read-only memories (ROM) in order to provide the code translation in both the encoder and in the decoder. A flag signal was also generated and fed forward, latched, and then fed back in order to change ROM addressing whenever a six bit code word combination was required by the coding process in order to be sure that the three to two code did not result in adjacent binary ONEs in the code word bit stream. The use of separate encoder and decoder apparatus added to the complexity and cost of that implementation, and the use of look up tables stored in ROM meant that large scale integration of that apparatus on a single chip was cumbersome and difficult. Also, circuit elements performing similar functions were duplicated in the separate encoder and decoder, with little or no thought given to combining of functions into common circuit elements to promote efficiency and to minimize topology required in an implementation based in a single very large scale integrated circuit.
Other prior art methods and apparatus for 1,7 coding processes are found in U.S. Pat. No. 4,413,251 which discloses an encoder and decoder which are separate structures, and U.S. Pat. No. 4,488,142, which also disoloses separate encoder and decoder structures. These prior art references have a number of differences and complexities made unnecessary by the present invention.